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…showed last 75 words of 582 total…threshold voltages and ruin the transistor. Leakage current is also reduced since there is no path for the carriers when the device is off. Many of these new transistor design techniques should take place within the next decade, depending on the application. For high power uses (i.e. microprocessors) planar CMOS will be used for much longer than more low power devices which should switch to double-gate devices since the leakage current is significantly less.